GCC

Makefiles

Make files are used to automate the compilation of multiple source files. The entire set of make and source files is called a project.

A Makefile contains the definition of the module names and associated compile options. From those definitions the make program knows how to invoke the GCC to compile each module of the project and create the final application.

Example Makefile: 

SRC = main.c a.c b.c ... # modules
PRG = main # executable

OBJ = $(SRC:%.c=%.o) # objects

all:	$(OBJ)
	$(CC) $(CFLAGS) $(OBJ) -o $(PRG) # link

%.o: %.c
	$(CC) $(CFLAGS) -I. -c $< -o $@ # compile

clean:
	$(RM) $(OBJ) $(PRG) *~ # remove

Use the above Makefile as a template for your own projects. Substitute the first line with the names of your own projects’ modules. Then type “make” on the console and the make program will create the corresponding executable.

When you change the source code during program development, the make program will determine unchanged modules and will only recompile and link the changed ones.

← gdb | ● | CMake →

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